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Integrated Circuit Systems, Inc.
ICS950227
Programmable Timing Control HubTM for P4TM
Recommended Application: CK-408 clock Intel(R) 845 with P4 processor. Output Features: * 3 Differential CPU Clock Pairs @ 3.3V * 7 PCI (3.3V) @ 33.3MHz * 3 PCI_F (3.3V) @ 33.3MHz * 1 USB (3.3V) @ 48MHz * 1 DOT (3.3V) @ 48MHz * 1 REF (3.3V) @ 14.318MHz * 5 3V66 (3.3V) @ 66.6MHz * 1 VCH/3V66 (3.3V) @ 48MHz or 66.6MHz Features/Benefits: * Programmable output frequency. * Programmable output divider ratios. * Programmable output rise/fall time. * Programmable output skew. * Programmable spread percentage for EMI control. * Watchdog timer technology to reset system if system malfunctions. * Programmable watch dog safe frequency. * Support I2C Index read/write and block read/write operations. * Uses external 14.318MHz crystal. Key Specifications: * CPU Output Jitter <150ps * 3V66 Output Jitter <250ps * CPU Output Skew <100ps
Pin Configuration
VDDREF X1 X2 GND PCICLK_F0 PCICLK_F1 PCICLK_F2 VDDPCI GND PCICLK0 PCICLK1 PCICLK2 PCICLK3 VDDPCI GND PCICLK4 PCICLK5 PCICLK6 VDD3V66 GND 3V66_2 3V66_3 3V66_4 3V66_5 *PD# VDDA GND Vtt_PWRGD# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 REF FS1 FS0 CPU_STOP#* CPUCLKT0 CPUCLKC0 VDDCPU CPUCLKT1 CPUCLKC1 GND VDDCPU CPUCLKT2 CPUCLKC2 MULTSEL0* IREF GND FS2 48MHz_USB 48MHz_DOT VDD48 GND 3V66_1/VCH_CLK PCI_STOP#* 3V66_0 VDD3V66 GND SCLK SDATA
56-Pin 300-mil SSOP
* These inputs have 150K internal pull-up resistor to VDD.
Block Diagram
PLL2 48MHz_USB 48MHz_DOT X1 XTAL OSC 3V66_1/VCH_CLK REF PLL1 Spread Spectrum WDEN PD# CPU_STOP# PCI_STOP# MULTSEL0 FS (2:0) SDATA SCLK Vtt_PWRGD#
CPU DIVDER Stop
3 3
Frequency Table
FS2 FS1 FS0 0 0 0 0 Mid Mid Mid Mid 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 CPU (MHz) 66.66 100.00 200.00 133.33 Tristate TCLK/2 3V66 (MHz) 66.66 66.66 66.66 66.66 Tristate TCLK/4 66Buff[2:0] 3V66[4:2] (MHz) 66.66 66.66 66.66 66.66 Tristate TCLK/4 PCI_F PCI (MHz) 33.33 33.33 33.33 33.33 Tristate TCLK/8 Reserved Reserved
CPUCLKT (2:0) CPUCLKC (2:0) PCICLK (6:0) PCICLK_F (2:0) 3V66 (5:2,0)
PCI DIVDER
Stop
7 3
Control Logic
3V66 DIVDER
Reserved Reserved Reserved Reserved Reserved Reserved
5
Config. Reg. I REF
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ICS950227
Integrated Circuit Systems, Inc.
ICS950227
Pin Description
PIN NUMBER
1, 8, 14, 19, 26, 32, 37, 46, 50 2 3 7, 6, 5 4, 9, 15, 20, 27, 31, 36, 41, 47 18, 17, 16, 13, 12,11, 10 24, 23, 22, 21 25
PIN NAME
VDD X1 X2
TYPE
PWR 3.3V power supply
DESCRIPTION
X2 Cr ystal 14.318MHz Cr ystal input Input X1 Cr ystal 14.318MHz Cr ystal output Output
PCICLK_F (2:0)
GND PCICLK (6:0) 3V66 (5:2) PD#
OUT
PWR OUT OUT IN
Free running PCI clock not affected by PCI_STOP# for power management.
Ground pins for 3.3V supply PCI clock outputs 66MHz reference clocks, from internal VCO Invokes power-down mode. Active Low.
28
Vtt_PWRGD#
IN I/O IN
OUT IN OUT OUT OUT IN OUT IN OUT OUT IN IN OUT
This 3.3V LVTTL input is a level sensitive strobe used to determine when FS(2:0) and MULTISEL0 inputs are valid and are ready to be sampled (active low) Data pin for I2C circuitr y 5V tolerant Clock pin of I2C circuitr y 5V tolerant
66MHz reference clocks, from internal VCO Halts PCICLK clocks at logic 0 level, when input low except PCICLK_F which are free running 3.3V output selectable through I2C to be 66MHz from internal VCO or 48MHz (non-SSC) 48MHz output clock for DOT 48MHz output clock for USB Special 3.3V input for Mode selection, cannot be logic 1 This pin establishes the reference current for the CPUCLK pairs. This pin requires a fixed precision resistor tied to ground in order to establish the appropriate current. 3.3V LVTTL input for selecting the current multiplier for CPU outputs "Complementor y" clocks of differential pair CPU outputs. These are current outputs and external resistors are required for voltage bias. "True" clocks of differential pair CPU outputs. These are current outputs and external resistors are required for voltage bias. Halts CPUCLK clocks at logic 0 level, when input low Frequency select pins 14.318MHz reference clock.
29 30 33 34 35 38 39 40 42 43 44, 48, 51 45, 49, 52 53 55, 54 56
SDATA SCLK 3V66_0 PCI_STOP# 3V66_1/VCH_CLK 48MHz_DOT 48MHz_USB FS2 I REF MULTSEL0 CPUCLKC (2:0) CPUCLKT (2:0) CPU_STOP# FS (1:0) REF
Power Groups (Analog)
VDDA = Analog Core PLL1 VDDREF = REF, Xtal VDD48 = 48MHz, PLL
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(Digital)
VDDPCI VDD3V66 VDDCPU
2
Integrated Circuit Systems, Inc.
ICS950227
Truth Table
FS2 0 0 0 0 Mid Mid Mid Mid FS1 0 0 1 1 0 0 1 1 FS0 0 1 0 1 0 1 0 1 CPU (MHz) 66.66 100.00 200.00 133.33 Tristate TCLK/2 3V66 (5:0) (MHz) 66.66 66.66 66.66 66.66 Tristate TCLK/4 PCI_F PCI (MHz) 33.33 33.33 33.33 33.33 Tristate TCLK/8 Reserved Reserved REF0 (MHz) 14.318 14.318 14.318 14.318 Tristate TCLK Reserved Reserved USB/DOT (MHz) 48.00 48.00 48.00 48.00 Tristate TCLK/2 Reserved Reserved
Reserved Reserved Reserved Reserved
Maximum Allowed Current
Max 3.3V supply consumption Max discrete cap loads, Vdd = 3.465V All static inputs = Vdd or GND 40mA 360mA
Condition Powerdown Mode (PWRDWN# = 0) Full Active
Host Swing Select Functions
Board Target Trace/Term Z 50 ohms Reference R, Iref = VDD/(3*Rr) Rr = 475 1%, Iref = 2.32mA Output Current Ioh = 6* I REF
MULTISEL0
Voh @ Z
1
0.7V @ 50
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ICS950227
General I2C serial interface information How to Write:
Controller (host) sends a start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends the begining byte location = N ICS clock will acknowledge Controller (host) sends the data byte count = X ICS clock will acknowledge Controller (host) starts sending Byte N through Byte N + X -1 (see Note 2) * ICS clock will acknowledge each byte one at a time * Controller (host) sends a Stop bit * * * * * * * *
How to Read:
* * * * * * * * * * * * * * Controller (host) will send start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends the begining byte location = N ICS clock will acknowledge Controller (host) will send a separate start bit. Controller (host) sends the read address D3 (H) ICS clock will acknowledge ICS clock will send the data byte count = X ICS clock sends Byte N + X -1 ICS clock sends Byte 0 through byte X (if X(H) was written to byte 8). Controller (host) will need to acknowledge each byte Controllor (host) will send a not acknowledge bit Controller (host) will send a stop bit
Index Block Write Operation
Controller (Host) starT bit T Slave Address D2(H) WR WRite Beginning Byte = N ACK Data Byte Count = X ACK Beginning Byte N ACK X Byte ICS (Slave/Receiver)
Index Block Read Operation
Controller (Host) T starT bit Slave Address D2(H) WR WRite Beginning Byte = N ACK RT Repeat starT Slave Address D3(H) RD ReaD ACK Data Byte Count = X ACK Beginning Byte N ACK X Byte ICS (Slave/Receiver)
ACK
ACK
Byte N + X - 1 ACK P stoP bit
Byte N + X - 1 N P Not acknowledge stoP bit
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Integrated Circuit Systems, Inc.
ICS950227
I C Table: Frequency Select Register
Byte 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 35 53 34 40 55 54 Pin # Control Function Frequency H/W IIC SPREAD ENABLE Select CENTER/DOWNSP CENTER/DOWNSPRE READ SELECT AD SELECT 3V66/VCH SELECT 48MHz/66.66MHz SEL CPU_STOP# PCI_STOP# HW/SW SELECT FS2 FS1 FS0 CPU STOP Read Back Freq Select Bit 3 Freq Select 2 Read Back Freq Select 1 Read Back Freq Select 0 Read Back Name Type RW RW RW R RW/R R R R READBACK 0 OFF DOWN SPREAD 66.66MHz 1 ON CENTER SPREAD 48.00MHz PWD 0 0 0 X 1 X X X
2
READBACK PCI STOP PCI RUNNING
I C Table: Spreading and Device Behavior Control Register
Byte 1 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 43 45, 44 49, 48 52, 51 45, 44 49, 48 52, 51 Pin # Name MULTSEL0 WD ALARM CPU2/CPUC2 CPU1/CPUC1 CPU0/CPUC0 CPU2/CPUC2 CPU1/CPUC1 CPU0/CPUC0 Output Control Output Control Output Control CPU FREE-RUN NING CONTROL Control Function MULTSEL0 READBACK Watchdog Alarm Read Back Type R R RW RW RW RW RW RW 0 READBACK NO ALARM ALARM SET STOPPABLE FREE-RUN STOPPABLE FREE-RUN STOPPABLE FREE-RUN Disable Disable Disable Enable Enable Enable 1 PWD X 0 0 0 0 1 1 1
2
I C Table: Output Control Register
Byte 2 Bit Bit Bit Bit Bit Bit Bit Bit 7 6 5 4 3 2 1 0 18 17 16 13 12 11 10 Pin # Name Reserved PCICLK6 PCICLK5 PCICLK4 PCICLK3 PCICLK2 PCICLK1 PCICLK0 Control Function Reserved Output Control Output Control Output Control Output Control Output Control Output Control Output Control Type RW RW RW RW RW RW RW RW 0 Disable Disable Disable Disable Disable Disable Disable 1 Enable Enable Enable Enable Enable Enable Enable PWD 0 1 1 1 1 1 1 1
2
I C Table: Output Control Register
Byte 3 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
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Pin # 38 39 7 6 5 7 6 5
Name 48MHz_DOT 48MHz_USB PCIF2 PCIF1 PCIF0 PCICLK_F2 PCICLK_F1 PCICLK_F0
Control Function Output Control Output Control
Type RW RW RW
0 Disable Disable
1 Enable Enable
PWD 1 1 0 0 0 1 1 1
FREE-RUN STOPPABLE FREE-RUN STOPPABLE FREE-RUN STOPPABLE Disable Disable Disable Enable Enable Enable
CPU FREE-RUN NING CONTROL
RW RW
Output Control Output Control Output Control
RW RW RW
5
Integrated Circuit Systems, Inc.
ICS950227
I C Table: Output Control Register
Byte 4 Bit Bit Bit Bit Bit Bit Bit Bit 7 6 5 4 3 2 1 0 33 35 24 23 22 21 Pin # Name RESERVED RESERVED 3V66_0 3V66_1/VHC_CLK 3V66_5 3V66_4 3V66_3 3V66_2 Control Function RESERVED RESERVED Output Control Output Control Output Control Output Control Output Control Output Control Type RW RW RW RW RW RW 0 Disable Disable Disable Disable Disable Disable 1 Enable Enable Enable Enable Enable Enable PWD 0 0 1 1 1 1 1 1
2
I C Table: Output Control and Fix Frequecy Register
Byte 5 Bit Bit Bit Bit Bit 7 6 5 4 3 38 Pin # Name RESERVED RESERVED RESERVED RESERVED 48MHz_DOT Control Function DOT CLOCK EDGE RATE CONTROL USB EDGE RATE CONTROL Type RW RW RW 39 48MHz_USB RW 0 1 PWD 0 0 0 0 0 0 0 0
2
Bit 2 Bit 1 Bit 0
00= MEDIUM (DEFAULT) 10= LOW 01= HIGH 00= MEDIUM (DEFAULT) 01= LOW 10= HIGH
I C Table: Vendor & Revision ID Register
Byte 6 Bit Bit Bit Bit Bit Bit Bit Bit 7 6 5 4 3 2 1 0 Pin # Name RID3 RID2 RID1 RID0 VID3 VID2 VID1 VID0 Control Function REVISION ID Type R R R R R R R R 0 1 PWD 1 1 1 1 1 1 1 1
2
VENDOR ID
I C Table: DEVICE ID
Byte 7 Bit Bit Bit Bit Bit Bit Bit Bit 7 6 5 4 3 2 1 0 Pin # Name Control Function Type R R R R R R R R 0 1 PWD 0 0 0 0 0 0 0 1
2
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Integrated Circuit Systems, Inc.
ICS950227
I C Table: Byte Count Register
Byte 8 Bit Bit Bit Bit Bit Bit Bit Bit 7 6 5 4 3 2 1 0 Pin # Name BC7 BC6 BC5 BC4 BC3 BC2 BC1 BC0 Control Function Writing to this register will configure how many bytes will be read back, default is 0F = 15 bytes. Type RW RW RW RW RW RW RW RW 0 1 PWD 0 0 0 0 1 1 1 1
2
I C Table: Watchdog Timer Register
Byte 9 Bit Bit Bit Bit Bit Bit Bit 7 6 5 4 3 2 1 Pin # Name RESERVED RESERVED RESERVED WD4 WD3 WD2 WD1 WD0 Control Function RESERVED RESERVED RESERVED These bits represent X*290ms the watchdog timer will wait before it goes to alarm mode. Default is10X 290ms =2.9seconds Type RW RW RW RW RW RW RW RW 0 1 PWD 0 0 0 0 1 0 1 0
2
Bit 0
I C Table: VCO Control Select Bit & WD Timer Control Register
Byte 10 Bit 7 Bit 6 Bit 5 Bit Bit Bit Bit Bit 4 3 2 1 0 Pin # Name M/NEN WDEN WDFSEN WD SS EN WD MultSEL WD FS2 WD FS1 WD FS0 Control Function M/N Programming Enable Watchdog Enable WD Safe Frequency Mode Writing to these bit will configure the safe frequency configuration Type RW RW RW RW RW RW RW RW 0 Latched Input OFF Latched FS/Byte0 1 IIC Prog. B(11:17) ON WD B10 b(4:0) PWD 0 0 0 0 0 0 0 0
2
I C Table: VCO Frequency Control Register
Bit Bit Bit Bit Bit Bit Bit Bit Byte 11 7 6 5 4 3 2 1 0 Pin # Name N Div8 M Div6 M Div5 M Div4 M Div3 M Div2 M Div1 M Div0 Control Function N Divider Bit 8 The decimal representation of M Div (6:0) is equal to reference divider value. Default at power up = latch-in or Byte 0 Rom table. Type RW RW RW RW RW RW RW RW 0 1 PWD X X X X X X X X
2
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Integrated Circuit Systems, Inc.
ICS950227
I C Table: VCO Frequency Control Register
Bit Bit Bit Bit Bit Bit Bit Bit Byte 12 7 6 5 4 3 2 1 0 Pin # Name N Div7 N Div6 N Div5 N Div4 N Div3 N Div2 N Div1 N Div0 Control Function The decimal representation of N Div (8:0) is equal to VCO divider value. Default at power up = latch-in or Byte 0 Rom table. Type RW RW RW RW RW RW RW RW 0 1 PWD X X X X X X X X
2
I C Table: Spread Spectrum Control Register
Bit Bit Bit Bit Bit Bit Bit Bit
2
2
Byte 13 7 6 5 4 3 2 1 0
Pin # -
Name SSP7 SSP6 SSP5 SSP4 SSP3 SSP2 SSP1 SSP0
Control Function These Spread Spectrum bits will program the spread pecentage. It is recommended to use ICS Spread % table for spread programming.
Type RW RW RW RW RW RW RW RW
0 -
1 -
PWD X X X X X X X X
I C Table: Spread Spectrum Control Register
Bit Bit Bit Bit Bit Bit Bit Bit Byte 14 7 6 5 4 3 2 1 0 Pin # Name Reserved Reserved SSP13 SSP12 SSP11 SSP10 SSP9 SSP8 Control Function Reserved Reserved It is recommended to use ICS Spread % table for spread programming. Type RW RW RW RW RW RW RW RW 0 1 PWD 0 0 X X X X X X
I C Table: Output Divider Control Register
Bit Bit Bit Bit Bit Bit Bit Bit Byte 15 7 6 5 4 3 2 1 0 Pin # Name Reserved Reserved Reserved Reserved CPU Div3 CPU Div2 CPU Div1 CPU Div0 Control Function Reserved Reserved Reserved Reserved CPU divider ratio can be configured via these 4 bits individually. Type RW RW RW RW RW RW RW RW 0 1 PWD 0 0 0 0 X X X X
2
See Table 3: Divider Ratio Combination Table 2-3-5-7
I C Table: Output Divider Control Register
Bit Bit Bit Bit Bit Bit Bit Bit Byte 16 7 6 5 4 3 2 1 0 Pin # Name Reserved Reserved Reserved Reserved 3V66 Div3 3V66 Div2 3V66 Div1 3V66 Div0 Control Function Reserved Reserved Reserved Reserved 3V66 divider ratio can be configured via these 4 bits individually. Type RW RW RW RW RW RW RW RW 0 1 PWD 0 0 0 0 X X X X
2
See Table 3: Divider Ratio Combination Table
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Integrated Circuit Systems, Inc.
ICS950227
I C Table: Output Divider Control Register
Bit Bit Bit Bit Bit Bit Bit Bit Byte 17 7 6 5 4 3 2 1 0 Pin # Name Reserved Reserved Reserved CPUINV Reserved Reserved Reserved Reserved Control Function Reserved Reserved Reserved CPU Phase Invert Reserved Reserved Reserved Reserved Type RW RW RW RW RW RW RW RW 0 Default 1 Inverse PWD 0 0 0 0 0 0 0 0
2
I C Table: Group Skew Control Register
Bit Bit Bit Bit Bit Bit Bit Bit Byte 18 7 6 5 4 3 2 1 0 Pin # Name Reserved Reserved Reserved Reserved CPUSkw1 CPUSkw0 Reserved Reserved Control Function Reserved Reserved Reserved Reserved CPUCLKT/C (2:0) Skew Control Reserved Reserved Type RW RW RW RW RW RW RW RW 0 1 PWD 0 0 0 0 0 1 0 0
2
I C Table: Group Skew Control Register
Bit Bit Bit Bit Bit Bit Bit Bit
2
2
Byte 19 7 6 5 4 3 2 1 0
Pin # -
Name Reserved Reserved Reserved Reserved PCISkw3 PCISkw2 PCISkw1 PCISkw0
Control Function Reserved Reserved Reserved Reserved PCI (6:1) AND PCIF(2:0) Skew Control
Type RW RW RW RW RW RW RW RW
0 1 16-Steps Skew Control. This byte will advance or delay the skew by 100ps per step
PWD 0 0 0 0 0 1 0 0
I C Table: Slew Rate Control Register
Byte 20 Bit 7 Bit 6 Bit Bit Bit Bit Bit Bit 5 4 3 2 1 0 Pin # Name 3V66ISkw 3V66ISkw Reserved Reserved RESERVED RESERVED RESERVED RESERVED Control Function 3V66 (5:0) Skew Control Reserved Reserved Reserved Reserved Reserved Reserved Type RW RW RW RW 0 1 Skew Control This byte will advance or delay the skew by 250 ps per step PWD 0 1 0 0 0 0 0 0
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Integrated Circuit Systems, Inc.
ICS950227
I C Table: Slew Rate Control Register
Byte 21 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 3V66SLW 3V66SLW PCISlw Pin # Name PCISlw Control Function PCICLK_F2 Slew Rate Control PCICLK_F1:0 Slew Rate Control 3V66 (5:2) Slew Rate Control 3V66 (1:0) Slew Rate Control Type RW 0 1 10=STRONG 00= MEDIUM 01= WEAK 10=STRONG 00= MEDIUM 01= WEAK 10=STRONG 00= MEDIUM 01= WEAK 10=STRONG 00= MEDIUM 01= WEAK PWD 1 0 1 0 1 0 1 0
2
RW
RW
RW
I C Table: Slew Rate Control Register
Byte 22 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # Name PCISlw Control Function REF Slew Rate Control PCICLK (6:4) Slew Rate Control PCICLK (3:1) Slew Rate Control PCICLK0 Slew Rate Control Type RW RW PCISlw RW RW RW RW RW RW 0 1 10=STRONG 00= MEDIUM 01= WEAK 10=STRONG 00= MEDIUM 01= WEAK 10=STRONG 00= MEDIUM 01= WEAK 10=STRONG 00= MEDIUM 01= WEAK PWD 1 0 1 0 1 0 1 0
2
PCISlw
PCISlw
I C Table: Slew Rate Control Register
Byte 23 Bit 7 Bit 7 Bit 6 Bit 5 Bit 4 Bit Bit Bit Bit 3 2 1 0 Pin # Name PCISlw1 Reserved Reserved VCSLW Reserved Reserved Reserved Reserved Control Function PCI (6:4) Slew Rate Control Reserved Reserved VCH Slew Rate Control Reserved Reserved Reserved Reserved Type RW RW RW RW RW RW RW RW RW 0 1 PWD 1 0 0 1 0 0 0 0 0
2
10=STRONG 00= MEDIUM 01= WEAK -
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Integrated Circuit Systems, Inc.
ICS950227
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND -0.5 V to VDD +0.5 V Ambient Operating Temperature . . . . . . . . . . . . 0C to +70C Case Temperature . . . . . . . . . . . . . . . . . . . . . . . . 115C Storage Temperature . . . . . . . . . . . . . . . . . . . . . -65C to +150C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70C; Supply Voltage VDD = 3.3 V +/-5% PARAMETER SYMBOL Input High Voltage Input Low Voltage Input High Current V IH V IL IIH I IL1 Input Low Current I IL2 Operating Supply Current Powerdown Current Input Frequency Pin Inductance Input Capacitance1 Clk Stabilization1,2 IDD3.3OP IDD3.3PD Fi Lpin CIN COUT CINX TSTAB tPZH,tPZL Delay 1 tPHZ,tPLZ
1 2
CONDITIONS
MIN 2 VSS - 0.3 -5 -5 -200
TYP
MAX V DD + 0.3 0.8 5
UNITS V V mA mA
V IN = VDD VIN = 0 V; Inputs with no pull-up resistors VIN = 0 V; Inputs with pull-up resistors CL = Full load IREF=2.32 mA VDD = 3.3 V Logic Inputs Output pin capacitance X1 & X2 pins From PowerUp or deassertion of PowerDown to 1st clock. Output enable delay (all outputs) Output disable delay (all outputs)
283 23 14.32
360 25 7 5 6 45 1.8
mA mA MHz nH pF pF pF ms ns ns
27
1 1
10 10
Guaranteed by design, not 100% tested in production. See timing diagrams for buffered and un-buffered timing requirements.
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ICS950227
Electrical Characteristics - CPU 0.7V Current Mode Differential Pair
TA = 0 - 70C; VDD = 3.3 V +/-5%; CL =2pF PARAMETER Current Source Output Impedance Voltage High Voltage Low Max Voltage Min Voltage Crossing Voltage (abs) Crossing Voltage (var) Long Accuracy SYMBOL Zo1 VHigh VLow Vovs Vuds Vcross(abs) d-Vcross ppm CONDITIONS VO = Vx Statistical measurement on single ended signal using oscilloscope math function. Measurement on single ended signal using absolute value. Variation of crossing over all edges see Tperiod min-max values 200MHz nominal 200MHz spread 166.66MHz nominal 166.66MHz spread 133.33MHz nominal 133.33MHz spread 100.00MHz nominal 100.00MHz spread 200MHz nominal 166.66MHz nominal/spread 133.33MHz nominal/spread 100.00MHz nominal/spread VOL = 0.175V, VOH = 0.525V VOH = 0.525V VOL = 0.175V MIN 3000 660 -150 -300 250 770 5 756 -7 350 12 -300 4.9985 4.9985 5.9982 5.9982 7.4978 7.4978 9.9970 9.9970 4.8735 5.8732 7.3728 9.8720 175 175 850 mV 150 1150 550 140 300 5.0015 5.0266 6.0018 6.0320 7.5023 5.4000 10.0030 10.0533 mV mV mV ppm ns ns ns ns ns ns ns ns ns ns ns ns ps ps ps ps 1 1 1 1 1 1,2 2 2 2 2 2 2 2 2 1,2 1,2 1,2 1,2 1 1 1 1 1 1 1 TYP MAX UNITS NOTES 1 1
Average period
Tperiod
Absolute min period Rise Time Fall Time Rise Time Variation Fall Time Variation Duty Cycle
Tabsmin tr tf d-tr d-tf dt3
332 344 30 30
700 700 125 125
Measurement from differential 45 49 55 % wavefrom tsk3 VT = 50% Skew 8 100 ps Measurement from differential tjcyc-cyc 60 150 ps Jitter, Cycle to cycle wavefrom 1 Guaranteed by design, not 100% tested in production. 2 All Long Term Accuracy and Clock Period specifications are guaranteed with the assumption that Ref output is at 14.31818MHz
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Integrated Circuit Systems, Inc.
ICS950227
Electrical Characteristics - 3V66 [5:0]
TA = 0 - 70C; VDD=3.3V +/-5%; CL = 10-30 pF (unless otherwise specified) PARAMETER SYMBOL CONDITIONS Output Frequency FO Output Impedance VO = VDD*(0.5) RDSP11 1 Output High Voltage I OH = -1 mA VOH Output Low Voltage Output High Current Output Low Current Rise Time Fall Time Duty Cycle Skew Jitter
1
MIN 12 2.4
TYP 66.66
MAX 55 0.55
UNITS MHz V V mA mA ns ns % ps ps
VOL1 I OH1 I OL1 t r11 t f11 dt11 t sk11 t jcyc-cyc
1
I OL = 1 mA V OH@MIN = 1.0 V, V OH@MAX = 3.135 V VOL @MIN = 1.95 V, VOL @MAX = 0.4 V VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V VT = 1.5 V 3V66
-33 30 0.5 0.5 45
-110 -20 110 37 1.8 1.3 51.2 136 241
-33 38 2 2 55 250 250
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - PCICLK
TA = 0 - 70C; VDD=3.3V +/-5%; CL = 10-30 pF (unless otherwise specified) PARAMETER SYMBOL CONDITIONS Output Frequency FO Output Impedance VO = VDD*(0.5) RDSP11 1 Output High Voltage I OH = -1 mA VOH Output Low Voltage Output High Current Output Low Current Rise Time Fall Time Duty Cycle Skew Jitter,cycle to cyc
1
MIN 12 2.4 -33 30 0.5 0.5 45
TYP 33.33 3.28 0.08 -110 -20 110 37 1.51 1.32 51.1 101 226
MAX 55 0.55 -33 38 2 2 55 500 250
UNITS MHz V V mA mA ns ns % ps ps
VOL1 I OH1 I OL1 t r11 t f11 dt11 t sk11 t jcyc-cyc
1
I OL = 1 mA VOH@MIN = 1.0 V, V OH@MAX = 3.135 V VOL@MIN = 1.95 V, VOL @MAX = 0.4 V VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V VT = 1.5 V
Guaranteed by design, not 100% tested in production.
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Integrated Circuit Systems, Inc.
ICS950227
Electrical Characteristics - VCH, 48MHz DOT, 48MHz, USB
TA = 0 - 70C; VDD=3.3V +/-5%; CL = 10-20 pF (unless otherwise specified) PARAMETER SYMBOL CONDITIONS Output Frequency FO Output Impedance VO = VDD*(0.5) RDSP11 1 IOH = -1 mA Output High Voltage VOH Output Low Voltage Output High Current Output Low Current 48DOT Rise Time 48DOT Fall Time VCH 48 USB Rise Time VCH 48 USB Fall Time 48 DOT Duty Cycle VCH 48 USB Duty Cycle 48 DOT Jitter USB to DOT Skew VCH Jitter
1
MIN 20 2.4 -29
TYP 48.008 3.27
MAX 60 0.4
UNITS MHz V V mA mA ns ns ns ns % % ps ns ps
VOL
1
I OH1 I OL1 tr11 tf11 tr11 tf11 dt11 dt11 tjcyc-cyc tsk11 tjcyc-cyc
1 1
IOL = 1 mA V OH@MIN = 1.0 V, V OH@MAX = 3.135 V VOL @MIN = 1.95 V, VOL @MAX = 0.4 V VOL = 0.4 V, V OH = 2.4 V VOH = 2.4 V, V OL = 0.4 V VOL = 0.4 V, V OH = 2.4 V VOH = 2.4 V, V OL = 0.4 V VT = 1.5 V VT = 1.5 V VT = 1.5 V V T = 1.5 V (0 OR 180 degrees) VT = 1.5 V
-61 -12
-23 27
29 0.5 0.5 1 1 45 45 0.84 0.92 1.74 1.84 53.2 52.5 151 0.53 187
1 1 2 2 55 55 350 1 350
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - REF
TA = 0 - 70C; VDD=3.3V +/-5%; CL = 10-20 pF (unless otherwise specified) PARAMETER SYMBOL CONDITIONS Output Frequency FO1 Output Impedance V O = V DD*(0.5) RDSP11 1 I OH = -1 mA Output High Voltage VOH Output Low Voltage Output High Current Output Low Current Rise Time Fall Time Duty Cycle Jitter
1
MIN 20 2.4 -33 30 1 1 45
TYP 14.318 3.28
MAX 60 0.4
UNITS MHz V V mA mA ns ns % ps
VOL
1
IOL = 1 mA V OH@MIN = 1.0 V V OH@MAX = 3.135 V VOL @MIN = 1.95 V VOL @MAX = 0.4 V VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V
1
IOH1 IOL1 t r11 t f11 dt11 tjcyc-cyc
-110 -20 110 37 1.38 1.31 54.7 276
-33 38 2 2 55 1000
VT = 1.5 V
Guaranteed by design, not 100% tested in production.
0641D--07/03/03
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Integrated Circuit Systems, Inc.
ICS950227
3V66 & PCI Phase Relationship All 3V66 clocks are to be in pphase with each other. In the case where 3V66_1 is configured as 48MHz VCH clock, there is no defined phase relationship between 3V66_1/VCH and other 3V66 clocks. The PCI group should lag 3V66 by the standard skew described below as Tpci.
3V66 (1:0) 3V66 (4:2) 3V66_5 PCICLK_F (2:0) PCICLK (6:0) Tpci
Group Skews at Common Transition Edges
GROUP 3V66 PCI 3V66 to PCI
1
SYMBOL 3V66 PCI S3V66-PCI
CONDITIONS 3V66 (5:0) pin to pin skew PCI_F (2:0) and PCI (6:0) pin to pin skew 3V66 (5:0) leads 33MHz PCI
MIN 0 0 1.5
TYP 136 101 2.08
MAX 250 500 3.5
UNITS ps ps ns
Guarenteed by design, not 100% tested in production.
PD# Functionality
CPU_STOP# 1 0
CPUT Normal iref * Mult
CPUC Normal Float
3V66 66MHz Low
66MHz_OUT 66MHz_IN Low
PCICLK_F PCICLK 66MHz_IN Low
PCICLK 66MHz_IN Low
USB/DOT 48MHz 48MHz Low
0641D--07/03/03
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Integrated Circuit Systems, Inc.
ICS950227
PCI_STOP# - Assertion (transition from logic "1" to logic "0")
The impact of asserting the PCI_STOP# signal will be the following. All PCI[6:0] and stoppable PCI_F[2,0] clocks will latch low in their next high to low transition. The PCI_STOP# setup time tsu is 10 ns, for transitions to be recognized by the next rising edge. Assertion of PCI_STOP# Waveforms
PCI_STOP# PCI_F[2:0] 33MHz PCI[6:0] 33MHz
tsu
CPU_STOP# - Assertion (transition from logic "1" to logic "0") The impact of asserting the CPU_STOP# pin is all CPU outputs that are set in the I2C configuration to be stoppable via assertion of CPU_STOP# are to be stopped after their next transition following the two CPU clock edge sampling as shown. The final state of the stopped CPU signals is CPUT=High and CPUC=Low. There is to be no change to the output drive current values. The CPUT will be driven high with a current value equal to (MULTSEL0) X (I REF), the CPUC signal will not be driven. Assertion of CPU_STOP# Waveforms
CPU_STOP# CPUT CPUC
CPU_STOP# Functionality
CPU_STOP# 1 0
CPUT Normal iref * Mult
CPUC Normal Float
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Integrated Circuit Systems, Inc.
ICS950227
N
c
SYMBOL
L
INDEX AREA
E1
E
12 D h x 45
A A1 b c D E E1 e h L N
In Millimeters COMMON DIMENSIONS MIN MAX 2.41 2.80 0.20 0.40 0.20 0.34 0.13 0.25 SEE VARIATIONS 10.03 10.68 7.40 7.60 0.635 BASIC 0.38 0.64 0.50 1.02 SEE VARIATIONS 0 8 VARIATIONS D mm. MIN MAX 18.31 18.55
In Inches COMMON DIMENSIONS MIN MAX .095 .110 .008 .016 .008 .0135 .005 .010 SEE VARIATIONS .395 .420 .291 .299 0.025 BASIC .015 .025 .020 .040 SEE VARIATIONS 0 8
A A1
N
-C-
D (inch) MIN .720 MAX .730
56
10-0034
e
b
SEATING PLANE .10 (.004) C
Reference Doc.: JEDEC Publication 95, MO-118
300 mil SSOP Package
Ordering Information
ICS950227yFT
Example:
ICS XXXXXX y F - T
Designation for tape and reel packaging Package Type F = SSOP Revision Designator (will not correlate with datasheet revision) Device Type Prefix ICS = Standard Device
0641D--07/03/03
17

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